1. Field of the Invention
The present invention relates to the semiconductor device with a spacer, and more particularly to the structure of the spacer against a gate in MOSFET.
2. Description of the Prior Art
It has been determined that hot-carrier effects will cause unacceptable performance degradation in NMOS devices built with conventional drain structures if their channel lengths are less than 2 .mu.m. To overcome this problem, such alternative drain structures as lightly doped drains (LDDs) must used.
In the LDD structure, the drain is formed by an implant self-aligned to the gate electrode, and the other is self-aligned to the gate electrode on which two oxide sidewall spacers have been formed. The purpose of the lighter first dose is to form a lightly doped section of the drain at the edge near the channel. In NMOS devices, this dose is normally 1-2.times.10.sup.13 atoms/cm.sup.2 of phosphorus.
In the conventional fabrication of MOSFET, to form a gate, resist and etching are used after the metal-oxide-semiconductor (MOS) layer is formed. Unfortunately, solvent used to strip the resist will erode the sidewall of the gate to lead to a narrower width and higher electric resistance. In the following implantation for LDD, the exposing sidewall of a gate is attacked by the ions going to be implanted into the substrate. The emancipated metal particles, such as Ti, will pollute the chamber of machine. Moreover, during the stripping of photoresist used for the LDD implantation, the sidewall of the gate will be eroded, too. Therefore, the quality of products and the efficiency of fabrication will be both reduced.
For the foregoing reasons, there is a need for solving the pollution of the machine and the high electric resistance of gates to enhance both the quality of products and the efficiency of fabrication.